This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant program and data trace compression using a low complexity messaging framework. The architecture targets System-on-Chip designs with multiple processor cores. The novel debug support is attached through defined interfaces making intellectual property re-use more practical. Synthesis to standard cells shows that the approach is more compact than conventional solutions. Extensions to the overviewed architecture are then proposed to allow support for both reconfigurable circuits and hybrid circuits that contain a mixture of reconfigurable and static cores.