Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Bratislava, Slovak Republic July 10-July 13 ISBN: 0-7695-2902-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACSD.2007.54
With the advance in semiconductor technology we are able to pack more and more devices on a single chip [5]. However, the threat comes from the long interconnect wires [6] whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency due the long interconnects, we require the IP cores to be latency-insensitive (LI). Design and validation of LI design is studied in [1, 2, 11]. Generalised latency-insensitive systems, design of connecting FIFOs and other communication protocols appear in [3, 4, 8, 10].
Citation:
Hemangee K. Kapoor, "Modelling Latency-Insensitive Systems in CSP," acsd, pp.231-232, Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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