With the advance in semiconductor technology we are able to pack more and more devices on a single chip [5]. However, the threat comes from the long interconnect wires [6] whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency due the long interconnects, we require the IP cores to be latency-insensitive (LI). Design and validation of LI design is studied in [1, 2, 11]. Generalised latency-insensitive systems, design of connecting FIFOs and other communication protocols appear in [3, 4, 8, 10].