This paper presents new approaches for high-level synthesis of highly concurrent hardware systems modeled with timed marked graphs. Unlike control data flow graphs (CDFGs) used in most high-level synthesis works, timed marked graphs can easily express highly concurrent hardware systems, including those with pipelined and multithreading behaviors. We first propose both exact and heuristic scheduling and allocation algorithms without considering binding. These algorithms, however, do not allow the cost associated with binding to be included. Thus, we propose concurrent scheduling and binding algorithms that include control complexity. Lastly, we describe and compare experimental results on a variety of digital signal processing (DSP) applications.