Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Hemangee Kapoor Articles by Mark Josephs

Fifth International Conference on Application of Concurrency to System Design (ACSD'05)

St. Malo, France

June 07-June 09

ISBN: 0-7695-2363-3

	ASCII Text	x
	Hemangee Kapoor, Mark Josephs, "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation," Application of Concurrency to System Design, International Conference on, pp. 58-67, Fifth International Conference on Application of Concurrency to System Design (ACSD'05), 2005.

	BibTex	x
	@article{ 10.1109/ACSD.2005.9, author = {Hemangee Kapoor and Mark Josephs}, title = {Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation}, journal ={Application of Concurrency to System Design, International Conference on}, volume = {0}, year = {2005}, issn = {1550-4808}, pages = {58-67}, doi = {http://doi.ieeecomputersociety.org/10.1109/ACSD.2005.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application of Concurrency to System Design, International Conference on TI - Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation SN - 1550-4808 SP58 EP67 A1 - Hemangee Kapoor, A1 - Mark Josephs, PY - 2005 KW - null VL - 0 JA - Application of Concurrency to System Design, International Conference on ER -

Hemangee Kapoor, Dhirubhai Ambani Institute of Information and Communication Technology

Mark Josephs, Centre for Concurrent Systems and VLSI

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACSD.2005.9

Delay-insensitive processes are typically implemented as asynchronous logic blocks; the possibility of transmission interference along the wires that connect them is considered to be a design error. Using DI-Algebra, the concepts of controllability, reflection, testing by interaction, and design by factorisation are explored. In general, a controllable process should be twice reflected so as to make it as abstract as possible.

Citation:

Hemangee Kapoor, Mark Josephs, "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation," acsd, pp.58-67, Fifth International Conference on Application of Concurrency to System Design (ACSD'05), 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.