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22nd Annual Computer Security Applications Conference (ACSAC'06)
Covert and Side Channels Due to Processor Architecture
Miami Beach, Florida, USA
December 11-December 15
ISBN: 0-7695-2716-7
Zhenghong Wang, Princeton University
Ruby B. Lee, Princeton University
Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show how processor architecture features such as simultaneous multithreading, control speculation and shared caches can inadvertently accelerate such covert channels or enable new covert channels and side channels. We first illustrate the reality and severity of this problem by describing concrete attacks. We identify two new covert channels. We show orders of magnitude increases in covert channel capacities. We then present two solutions, Selective Partitioning and the novel Random Permutation Cache (RPCache). The RPCache can thwart most cache-based software side channel attacks, with minimal hardware costs and negligible performance impact.
Citation:
Zhenghong Wang, Ruby B. Lee, "Covert and Side Channels Due to Processor Architecture," acsac, pp.473-482, 22nd Annual Computer Security Applications Conference (ACSAC'06), 2006
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