Retargetable Cache Simulation Using High Level Processor Models

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Rajiv Ravindran Articles by Rajat Moona

6th Australasian Computer Systems Architecture Conference (AustCSAC'01)

Gold Coast, Queensland, Australia

January 29-January 30

ISBN: 0-7695-0954-1

	ASCII Text	x
	Rajiv Ravindran, Rajat Moona, "Retargetable Cache Simulation Using High Level Processor Models," Australasian Computer Systems Architecture Conference, pp. 114, 6th Australasian Computer Systems Architecture Conference (AustCSAC'01), 2001.

	BibTex	x
	@article{ 10.1109/ACAC.2001.903371, author = {Rajiv Ravindran and Rajat Moona}, title = {Retargetable Cache Simulation Using High Level Processor Models}, journal ={Australasian Computer Systems Architecture Conference}, volume = {0}, year = {2001}, issn = {1530-0927}, pages = {114}, doi = {http://doi.ieeecomputersociety.org/10.1109/ACAC.2001.903371}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Australasian Computer Systems Architecture Conference TI - Retargetable Cache Simulation Using High Level Processor Models SN - 1530-0927 SP EP A1 - Rajiv Ravindran, A1 - Rajat Moona, PY - 2001 VL - 0 JA - Australasian Computer Systems Architecture Conference ER -

Rajiv Ravindran, Indian Institute of Technology

Rajat Moona, Indian Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACAC.2001.903371

During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator.The cache simulator has been implemented using a retargetable instruction set simulator from the Sim-nML [9] processor description language. The retargetability helps in cache simulation and evaluation much before the actual processor design.

Citation:

Rajiv Ravindran, Rajat Moona, "Retargetable Cache Simulation Using High Level Processor Models," austcsac, pp.114, 6th Australasian Computer Systems Architecture Conference (AustCSAC'01), 2001

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.