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Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
June 1999 (vol. 10 no. 6)
pp. 627-641
ASCII Text
x 
 
Z. Alkhalifa, V.s.s. Nair, N. Krishnamurthy, J.a. Abraham, "Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection," IEEE Transactions on Parallel and Distributed Systems, vol. 10, no. 6, pp. 627-641, June, 1999.
 
 
BibTex
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@article{ 10.1109/71.774911,
author = {Z. Alkhalifa and V.s.s. Nair and N. Krishnamurthy and J.a. Abraham},
title = {Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {10},
number = {6},
issn = {1045-9219},
year = {1999},
pages = {627-641},
doi = {http://doi.ieeecomputersociety.org/10.1109/71.774911},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IS - 6
SN - 1045-9219
SP627
EP641
EPD - 627-641
A1 - Z. Alkhalifa,
A1 - V.s.s. Nair,
A1 - N. Krishnamurthy,
A1 - J.a. Abraham,
PY - 1999
KW - Control flow checking
KW - assertions
KW - fault injection
KW - coverage
KW - latency.
VL - 10
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 

Abstract—This paper evaluates the concurrent error detection capabilities of system-level checks, using fault and error injection. The checks comprise application and system level mechanisms to detect control flow errors. We propose Enhanced Control-Flow Checking Using Assertions (ECCA). In ECCA, branch-free intervals (BFI) in a given high or intermediate level program are identified and the entry and exit points of the intervals are determined. BFIs are then grouped into blocks, the size of which is determined through a performance/overhead analysis. The blocks are then fortified with preinserted assertions. For the high level ECCA, we describe an implementation of ECCA through a preprocessor that will automatically insert the necessary assertions into the program. Then, we describe the intermediate implementation possible through modifications made on gcc to make it ECCA capable. The fault detection capabilities of the checks are evaluated both analytically and experimentally. Fault injection experiments are conducted using FERRARI [1] to determine the fault coverage of the proposed techniques.

[1] G.A. Kanawati, N.A. Kanawati, and J.A. Abraham, FERRARI: A Flexible Software-Based Fault and Error Injection System IEEE Trans. Computers, vol. 44, no. 2, pp. 248-260, Feb. 1995.[2] M. Lyu, Software Fault Tolerance. Willy, 1995.[3] G. Miremadi, J. Ohlsson, M. Rimen, and J. Karlsson, “Use of Time and Address Signatures for Control Flow Checking,” Fifth Int'l Working Conf. Dependable Computing for Critical Applications, Sept. 1995.[4] N. Saxena and E. McCluskey, "Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums," IEEE Trans. Computers, vol. 39, no. 4, pp. 554-558, Apr. 1990.[5] B. Ramamurthy and S.J. Upadhyaya, “Watchdog Processor-Assisted Fast Recovery in Distributed Systems,” Proc. Fifth Int'l Working Conf. Dependable Computing for Critical Applications, Sept. 1995.[6] M. Namjoo, “Techniques for Concurrent Testing of VLSI Processor Operation,” IEEE Trans. Computers, 1982.[7] A. Mahmood and E. McCluskey, "Concurrent Error Detection Using Watchdog Processors—A Survey," IEEE Trans. Computers, vol. 37, no. 2, pp. 160-174, Feb. 1988.[8] K. Wilken and J. Shen, "Continuous Signature Monitoring: Low-Cost Concurrent-Detection of Processor Control Errors," IEEE Trans. Computer-Aided Design, vol. 9, no. 3, pp. 629-641, June 1990.[9] D.J. Lu, “Watchdog Processors and Structural Integrity Checking,” IEEE Trans. Computers, July 1982.[10] L. Mcfearin and V.S.S. Nair, “Control-Flow Checking Using Assertions,” Proc. IFIP Int'l Working Conf. Dependable Computing for Critical Applications, Sept. 1995.[11] K. Kanawati, N. Krishnamurthy, S. Nair, and J.A. Abraham, “Evaluation of Integrated System-Level Checks for On-Line Error Detection,” Proc. IEEE Int'l Symp. Parallel and Distributed Systems, Sept. 1996.[12] K.H. Huang and J.A. Abraham, “Algorithm-Based Fault Tolerance for Matrix Operations,” IEEE Transactions on Computers, June 1984.[13] V.S.S. Nair and S. Venkatesan, “Algorithm-Based Fault Tolerance for Non-Computationally Intensive Applications,” Proc. SPIE Advanced Algorithms and Architectures for Signal Processing Conf., July 1994.[14] V.S.S. Nair, H. Kim, N. Krishnamurthy, and J.A. Abraham, “Design and Evaluation of Automated High-Level Checks for Signal Processing Applications,” Proc. SPIE Advanced Algorithms and Architectures for Signal Processing Conf., Aug. 1996.[15] A.V. Aho, R. Sethi, and J.D. Ullman, Compilers, Principles, Techniques and Tools.New York: Addison-Wesley, 1985.[16] D. Andrews, “Using Executable Assertions for Testing and Fault Tolerance,” Proc. Ninth Int'l Symp. Fault-Tolerant Computing, June 1979.[17] K.A. Hua, “Design of Systems with Concurrent Error Detection Using Software Redundancy,” PhD thesis, Univ. of Illinois, Urbana, 1987.[18] “Using and Porting GNU CC version 2,” Free Software Foundation, June 1991.[19] M. Namjoo, “Concurrent Testing Using Path Signature Analysis,” Stanford Univ. Technical Report CRC TR 82-16, 1982.

Index Terms:
Control flow checking, assertions, fault injection, coverage, latency.
Citation:
Z. Alkhalifa, V.s.s. Nair, N. Krishnamurthy, J.a. Abraham, "Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection," IEEE Transactions on Parallel and Distributed Systems, vol. 10, no. 6, pp. 627-641, June 1999, doi:10.1109/71.774911
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