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Multilevel Testing for Design Verification of Embedded Systems
March/April 2002 (vol. 19 no. 2)
pp. 60-69
ASCII Text
x 
 
Stephan Schulz, Jerzy W. Rozenbilt, Klaus J. Buchenrieder, "Multilevel Testing for Design Verification of Embedded Systems," IEEE Design and Test of Computers, vol. 19, no. 2, pp. 60-69, March/April, 2002.
 
 
BibTex
x
 
@article{ 10.1109/54.990443,
author = {Stephan Schulz and Jerzy W. Rozenbilt and Klaus J. Buchenrieder},
title = {Multilevel Testing for Design Verification of Embedded Systems},
journal ={IEEE Design and Test of Computers},
volume = {19},
number = {2},
issn = {0740-7475},
year = {2002},
pages = {60-69},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.990443},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Multilevel Testing for Design Verification of Embedded Systems
IS - 2
SN - 0740-7475
SP60
EP69
EPD - 60-69
A1 - Stephan Schulz,
A1 - Jerzy W. Rozenbilt,
A1 - Klaus J. Buchenrieder,
PY - 2002
VL - 19
JA - IEEE Design and Test of Computers
ER -
 

A multilevel testing approach for embedded systems addresses mixed hardware and software implementations. Contrary to conventional approaches, it provides consistent generation of scenarios throughout all levels of testing, an early assessment of alternative design implementations, integrated system and component testing, and performance assessments of design specifications starting from the system level.

Citation:
Stephan Schulz, Jerzy W. Rozenbilt, Klaus J. Buchenrieder, "Multilevel Testing for Design Verification of Embedded Systems," IEEE Design and Test of Computers, vol. 19, no. 2, pp. 60-69, Mar./Apr. 2002, doi:10.1109/54.990443
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