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Online Testing Approach for Very Deep-Submicron ICs
March/April 2002 (vol. 19 no. 2)
pp. 16-23
ASCII Text
x 
 
Michele Favalli, Cecilia Metra, "Online Testing Approach for Very Deep-Submicron ICs," IEEE Design and Test of Computers, vol. 19, no. 2, pp. 16-23, March/April, 2002.
 
 
BibTex
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@article{ 10.1109/54.990438,
author = {Michele Favalli and Cecilia Metra},
title = {Online Testing Approach for Very Deep-Submicron ICs},
journal ={IEEE Design and Test of Computers},
volume = {19},
number = {2},
issn = {0740-7475},
year = {2002},
pages = {16-23},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.990438},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Design and Test of Computers
TI - Online Testing Approach for Very Deep-Submicron ICs
IS - 2
SN - 0740-7475
SP16
EP23
EPD - 16-23
A1 - Michele Favalli,
A1 - Cecilia Metra,
PY - 2002
VL - 19
JA - IEEE Design and Test of Computers
ER -
 

Very deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these techniques to include gross-delay faults. Moreover, this approach can be exploited to detect stuck-at and bridging faults offline.

Citation:
Michele Favalli, Cecilia Metra, "Online Testing Approach for Very Deep-Submicron ICs," IEEE Design and Test of Computers, vol. 19, no. 2, pp. 16-23, Mar./Apr. 2002, doi:10.1109/54.990438
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