A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
January/February 2002 (vol. 19 no. 1)
pp. 18-28
ASCII Text
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Chouki Aktouf,
"A Complete Strategy for Testing an On-Chip Multiprocessor Architecture,"
IEEE Design and Test of Computers, vol. 19, no. 1, pp. 18-28, January/February, 2002.
BibTex
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@article{
10.1109/54.980050, author = {Chouki Aktouf}, title = {A Complete Strategy for Testing an On-Chip Multiprocessor Architecture}, journal ={IEEE Design and Test of Computers}, volume = {19}, number = {1}, issn = {0740-7475}, year = {2002}, pages = {18-28}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.980050}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Design and Test of Computers TI - A Complete Strategy for Testing an On-Chip Multiprocessor Architecture IS - 1 SN - 0740-7475 SP18 EP28 EPD - 18-28 A1 - Chouki Aktouf, PY - 2002 VL - 19 JA - IEEE Design and Test of Computers ER -
By dividing testing into three phases-router, RAM block, and processors-this strategy ensures an efficient tradeoff of test quality and cost.
Citation:
Chouki Aktouf, "A Complete Strategy for Testing an On-Chip Multiprocessor Architecture," IEEE Design and Test of Computers, vol. 19, no. 1, pp. 18-28, Jan./Feb. 2002, doi:10.1109/54.980050
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