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Strategies for Low-Cost Test
November/December 2001 (vol. 18 no. 6)
pp. 47-54
ASCII Text
x 
 
Rohit Kapur, R. Chandramouli, T.W. Williams, "Strategies for Low-Cost Test," IEEE Design and Test of Computers, vol. 18, no. 6, pp. 47-54, November/December, 2001.
 
 
BibTex
x
 
@article{ 10.1109/54.970423,
author = {Rohit Kapur and R. Chandramouli and T.W. Williams},
title = {Strategies for Low-Cost Test},
journal ={IEEE Design and Test of Computers},
volume = {18},
number = {6},
issn = {0740-7475},
year = {2001},
pages = {47-54},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.970423},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Strategies for Low-Cost Test
IS - 6
SN - 0740-7475
SP47
EP54
EPD - 47-54
A1 - Rohit Kapur,
A1 - R. Chandramouli,
A1 - T.W. Williams,
PY - 2001
VL - 18
JA - IEEE Design and Test of Computers
ER -
 

More collaboration between EDA, semiconductor, and ATE industry segments can improve the manufacturing test environment. These improvements can dramatically reduce the cost of test and lead to a new generation of DFT-aware ATE and ATE-aware DTE.

Citation:
Rohit Kapur, R. Chandramouli, T.W. Williams, "Strategies for Low-Cost Test," IEEE Design and Test of Computers, vol. 18, no. 6, pp. 47-54, Nov./Dec. 2001, doi:10.1109/54.970423
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