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Online and Offline BIST in IP-Core Design
September/October 2001 (vol. 18 no. 5)
pp. 92-99
ASCII Text
x 
 
Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bondoni, "Online and Offline BIST in IP-Core Design," IEEE Design and Test of Computers, vol. 18, no. 5, pp. 92-99, September/October, 2001.
 
 
BibTex
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@article{ 10.1109/54.953276,
author = {Alfredo Benso and Silvia Chiusano and Giorgio Di Natale and Paolo Prinetto and Monica Lobetti Bondoni},
title = {Online and Offline BIST in IP-Core Design},
journal ={IEEE Design and Test of Computers},
volume = {18},
number = {5},
issn = {0740-7475},
year = {2001},
pages = {92-99},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.953276},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Online and Offline BIST in IP-Core Design
IS - 5
SN - 0740-7475
SP92
EP99
EPD - 92-99
A1 - Alfredo Benso,
A1 - Silvia Chiusano,
A1 - Giorgio Di Natale,
A1 - Paolo Prinetto,
A1 - Monica Lobetti Bondoni,
PY - 2001
VL - 18
JA - IEEE Design and Test of Computers
ER -
 

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints.

Citation:
Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bondoni, "Online and Offline BIST in IP-Core Design," IEEE Design and Test of Computers, vol. 18, no. 5, pp. 92-99, Sep./Oct. 2001, doi:10.1109/54.953276
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