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Design and Test of Large Embedded Memories: An Overview
May/June 2001 (vol. 18 no. 3)
pp. 16-27
ASCII Text
x 
 
Rochit Rajsuman, "Design and Test of Large Embedded Memories: An Overview," IEEE Design and Test of Computers, vol. 18, no. 3, pp. 16-27, May/June, 2001.
 
 
BibTex
x
 
@article{ 10.1109/54.922800,
author = {Rochit Rajsuman},
title = {Design and Test of Large Embedded Memories: An Overview},
journal ={IEEE Design and Test of Computers},
volume = {18},
number = {3},
issn = {0740-7475},
year = {2001},
pages = {16-27},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.922800},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Design and Test of Large Embedded Memories: An Overview
IS - 3
SN - 0740-7475
SP16
EP27
EPD - 16-27
A1 - Rochit Rajsuman,
PY - 2001
VL - 18
JA - IEEE Design and Test of Computers
ER -
 
Large on-chip memories are desirable but difficult to implement. Challenges range from design automation to fabrication to test algorithms and memory redundancy and repair.
Citation:
Rochit Rajsuman, "Design and Test of Large Embedded Memories: An Overview," IEEE Design and Test of Computers, vol. 18, no. 3, pp. 16-27, May/June 2001, doi:10.1109/54.922800
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