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Power Management in the Amulet Microprocessors
March/April 2001 (vol. 18 no. 2)
pp. 42-52
ASCII Text
x 
 
Steve B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J.G. Lewis, Steve Temple, "Power Management in the Amulet Microprocessors," IEEE Design and Test of Computers, vol. 18, no. 2, pp. 42-52, March/April, 2001.
 
 
BibTex
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@article{ 10.1109/54.914617,
author = {Steve B. Furber and Aristides Efthymiou and Jim D. Garside and David W. Lloyd and Mike J.G. Lewis and Steve Temple},
title = {Power Management in the Amulet Microprocessors},
journal ={IEEE Design and Test of Computers},
volume = {18},
number = {2},
issn = {0740-7475},
year = {2001},
pages = {42-52},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.914617},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Power Management in the Amulet Microprocessors
IS - 2
SN - 0740-7475
SP42
EP52
EPD - 42-52
A1 - Steve B. Furber,
A1 - Aristides Efthymiou,
A1 - Jim D. Garside,
A1 - David W. Lloyd,
A1 - Mike J.G. Lewis,
A1 - Steve Temple,
PY - 2001
VL - 18
JA - IEEE Design and Test of Computers
ER -
 
Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity.
Citation:
Steve B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J.G. Lewis, Steve Temple, "Power Management in the Amulet Microprocessors," IEEE Design and Test of Computers, vol. 18, no. 2, pp. 42-52, Mar./Apr. 2001, doi:10.1109/54.914617
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