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Modeling a Verification Test System for Mixed-Signal Circuits
January/February 2001 (vol. 18 no. 1)
pp. 63-71
ASCII Text
x 
 
David San Segundo Bello, Ronald Tangelder, Hans Kerkhoff, "Modeling a Verification Test System for Mixed-Signal Circuits," IEEE Design and Test of Computers, vol. 18, no. 1, pp. 63-71, January/February, 2001.
 
 
BibTex
x
 
@article{ 10.1109/54.902823,
author = {David San Segundo Bello and Ronald Tangelder and Hans Kerkhoff},
title = {Modeling a Verification Test System for Mixed-Signal Circuits},
journal ={IEEE Design and Test of Computers},
volume = {18},
number = {1},
issn = {0740-7475},
year = {2001},
pages = {63-71},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.902823},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Modeling a Verification Test System for Mixed-Signal Circuits
IS - 1
SN - 0740-7475
SP63
EP71
EPD - 63-71
A1 - David San Segundo Bello,
A1 - Ronald Tangelder,
A1 - Hans Kerkhoff,
PY - 2001
VL - 18
JA - IEEE Design and Test of Computers
ER -
 
Modeling a commercial verification test system enables simulated tests to be performed before actual testing with instruments and enhances communication between designers and test engineers.
Citation:
David San Segundo Bello, Ronald Tangelder, Hans Kerkhoff, "Modeling a Verification Test System for Mixed-Signal Circuits," IEEE Design and Test of Computers, vol. 18, no. 1, pp. 63-71, Jan./Feb. 2001, doi:10.1109/54.902823
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