DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.867894
New design flows require reducing work at the gate level and perfoming most activities before the synthesis step, including evaluatation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach.
Citation:
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, "RT-Level ITC'99 Benchmarks and First ATPG Results," IEEE Design and Test of Computers, vol. 17, no. 3, pp. 44-53, July-Sept. 2000, doi:10.1109/54.867894 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||