DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.867892
This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods.
Citation:
Chouki Aktouf, Hérvé Fleury, Chantal Robach, "Inserting Scan at the Behavioral Level," IEEE Design and Test of Computers, vol. 17, no. 3, pp. 34-42, July-Sept. 2000, doi:10.1109/54.867892 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||