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Power Estimation of Digital Data Paths Using HEAT
April-June 2000 (vol. 17 no. 2)
pp. 101-110
ASCII Text
x 
 
Janardhan H. Satyanarayana, Keshab K. Parhi, "Power Estimation of Digital Data Paths Using HEAT," IEEE Design and Test of Computers, vol. 17, no. 2, pp. 101-110, April-June, 2000.
 
 
BibTex
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@article{ 10.1109/54.844339,
author = {Janardhan H. Satyanarayana and Keshab K. Parhi},
title = {Power Estimation of Digital Data Paths Using HEAT},
journal ={IEEE Design and Test of Computers},
volume = {17},
number = {2},
issn = {0740-7475},
year = {2000},
pages = {101-110},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.844339},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Power Estimation of Digital Data Paths Using HEAT
IS - 2
SN - 0740-7475
SP101
EP110
EPD - 101-110
A1 - Janardhan H. Satyanarayana,
A1 - Keshab K. Parhi,
PY - 2000
VL - 17
JA - IEEE Design and Test of Computers
ER -
 

The Hierarchical Energy Analysis Tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

Citation:
Janardhan H. Satyanarayana, Keshab K. Parhi, "Power Estimation of Digital Data Paths Using HEAT," IEEE Design and Test of Computers, vol. 17, no. 2, pp. 101-110, Apr.-June 2000, doi:10.1109/54.844339
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