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Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test
July/September 1991 (vol. 8 no. 3)
pp. 58-65
ASCII Text
x 
 
P. Nagvajara, M.G. Karpovsky, L.B. Levitin, "Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test," IEEE Design and Test of Computers, vol. 8, no. 3, pp. 58-65, July/September, 1991.
 
 
BibTex
x
 
@article{ 10.1109/54.84245,
author = {P. Nagvajara and M.G. Karpovsky and L.B. Levitin},
title = {Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test},
journal ={IEEE Design and Test of Computers},
volume = {8},
number = {3},
issn = {0740-7475},
year = {1991},
pages = {58-65},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.84245},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test
IS - 3
SN - 0740-7475
SP58
EP65
EPD - 58-65
A1 - P. Nagvajara,
A1 - M.G. Karpovsky,
A1 - L.B. Levitin,
PY - 1991
VL - 8
JA - IEEE Design and Test of Computers
ER -
 

The design of a pseudorandom pattern generator for a boundary-scan chip with built-in self-test is described. The proposed test-generation procedure, together with a method of connecting the generator outputs and the primary inputs of the chip under test, ensures full pattern coverage. The authors show how to evaluate the choice of generator parameters and initial states when there are more flip-flops in the generator than bits in the test pattern.

Citation:
P. Nagvajara, M.G. Karpovsky, L.B. Levitin, "Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test," IEEE Design and Test of Computers, vol. 8, no. 3, pp. 58-65, July 1991, doi:10.1109/54.84245
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