An approach to the electrical characterization of dynamic RAMs in which chip design and DRAM process technology are verified and optimized concurrently is reported. Both parametric and functional tests were performed. The authors describe an information and scheduling system for analysis and testing that handles the required electrical measuring data from the testers. It is shown how data analysis supports the interpretations by data correlations on a real statistical basis. The short learning cycle required by this approach was obtained by ensuring the smooth cooperation of all those involved in the overall analysis.