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The Compiled Logic Simulator
January/March 1991 (vol. 8 no. 1)
pp. 21-34
ASCII Text
x 
 
Brion Keller, David P. Carlson, William Maloney, "The Compiled Logic Simulator," IEEE Design and Test of Computers, vol. 8, no. 1, pp. 21-34, January/March, 1991.
 
 
BibTex
x
 
@article{ 10.1109/54.75660,
author = {Brion Keller and David P. Carlson and William Maloney},
title = {The Compiled Logic Simulator},
journal ={IEEE Design and Test of Computers},
volume = {8},
number = {1},
issn = {0740-7475},
year = {1991},
pages = {21-34},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.75660},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - The Compiled Logic Simulator
IS - 1
SN - 0740-7475
SP21
EP34
EPD - 21-34
A1 - Brion Keller,
A1 - David P. Carlson,
A1 - William Maloney,
PY - 1991
VL - 8
JA - IEEE Design and Test of Computers
ER -
 

A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator's compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The linear-feedback-shift-register simulation monitor is discussed. Performance results are presented. Fault simulation with one million random patterns on a 40000-gate circuit was done in 16 CPU minutes.

Citation:
Brion Keller, David P. Carlson, William Maloney, "The Compiled Logic Simulator," IEEE Design and Test of Computers, vol. 8, no. 1, pp. 21-34, Jan. 1991, doi:10.1109/54.75660
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