Rapid Hardware Prototyping on RPM-2 July-September 1998 (vol. 15 no. 3) pp. 112-118
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.706042
Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurability by software at low cost. Entire systems can be built in which some parts are programmable. Such systems implement various architectures. Each architecture prototype is a detailed hardware implementation of the architecture --including I/O-- on which complex software systems can be ported. We have built a multiprocessor emulator called RPM --Rapid Prototyping engine for Multiprocessor systems. The second version of the hardware called RPM-2 is up and running. In this article, we present the design and the performance of our first emulator, a cache-coherent non uniform memory access multiprocessor (CC-NUMA).
Index Terms:
FPGAs, architecture, multiprocessing, multiprocessor emulator
Citation:
Michel Dubois, Jaeheon Jeong, Yong Ho Song, Adrian Moga, "Rapid Hardware Prototyping on RPM-2," IEEE Design and Test of Computers, vol. 15, no. 3, pp. 112-118, July-Sept. 1998, doi:10.1109/54.706042 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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