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Test Strategy for the PowerPC 750 Microprocessor
July-September 1998 (vol. 15 no. 3)
pp. 90-97
ASCII Text
x 
 
Carol Pyron, Javier Prado, James Golab, "Test Strategy for the PowerPC 750 Microprocessor," IEEE Design and Test of Computers, vol. 15, no. 3, pp. 90-97, July-September, 1998.
 
 
BibTex
x
 
@article{ 10.1109/54.706039,
author = {Carol Pyron and Javier Prado and James Golab},
title = {Test Strategy for the PowerPC 750 Microprocessor},
journal ={IEEE Design and Test of Computers},
volume = {15},
number = {3},
issn = {0740-7475},
year = {1998},
pages = {90-97},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.706039},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Test Strategy for the PowerPC 750 Microprocessor
IS - 3
SN - 0740-7475
SP90
EP97
EPD - 90-97
A1 - Carol Pyron,
A1 - Javier Prado,
A1 - James Golab,
PY - 1998
KW - Microprocessor Test
KW - Design for Test
KW - LSSD
KW - Silicon Verification
VL - 15
JA - IEEE Design and Test of Computers
ER -
 
Time to market demands for the PowerPC 750 microprocessor require new test strategy approaches to improving the product test quality, reliability, and debug process. The total time to market includes not just the design cycle time to the initial tapeout, but also the productization time. Strong debug support and silicon verification are key to reducing the time to market. A test suite with high test effectiveness must be prepared before initial parts are available to minimize debug efforts on defective silicon. The implementation of the design for test and debug features also must be balanced with requirements for processor performance. The PowerPC 750 test strategy includes enhanced or new design for test features and improved test generation and debug processes
Index Terms:
Microprocessor Test, Design for Test, LSSD, Silicon Verification
Citation:
Carol Pyron, Javier Prado, James Golab, "Test Strategy for the PowerPC 750 Microprocessor," IEEE Design and Test of Computers, vol. 15, no. 3, pp. 90-97, July-Sept. 1998, doi:10.1109/54.706039
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