Design methodologies for digital integrated circuits are ultimately concerned with validating a design against metrics which ensure functionality, testability, and that the design satisfies power and timing requirements. Electronic design automation (EDA) tools and techniques have been developed to analyze each of these metrics. With technology scaling and increasing clock frequencies, noise and signal integrity are becoming important new design concerns in verifying functionality and accurately predicting timing. In this article, we describe a new metric for verifying functionality in the presence of noise, noise stability, and a static noise analysis methodology to verify it. In addition, we describe the effects of noise on delay and how these can be considered in the context of static timing analysis.