Applying an XC6200 to Real-Time Image Processing January-March 1998 (vol. 15 no. 1) pp. 30-38
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.655180
This article presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 Billion Multiplications or additions per second.
Index Terms:
FPGAs, Image compression, Custom Computing, distributed arithmetic
Citation:
Roger Woods, David Trainor, Jean-paul Heron, "Applying an XC6200 to Real-Time Image Processing," IEEE Design and Test of Computers, vol. 15, no. 1, pp. 30-38, Jan.-Mar. 1998, doi:10.1109/54.655180 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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