The delay models and costs analysis developed for ASIC technology are not useful for the design and implementation of fixed-point adders on FPGA devices. This paper discusses the implementation of fixed-point adders on the Xilinx 4k series devices and studies their related costs and operational delays. This work also proposes the timing models for the optimization analyses of the carry-skip and the carry-select adders and their optimization schemes. The comparison of the performances and costs of different fixed-point FPGA adders will be a useful source of information for the FPGA-based computing systems designers. The study should contribute to effective and cost-efficient designs of computational units on FPGA devices.