The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related to these clusters. There are three basic questions: how many look-up tables should a cluster contain, how should the flexibility of FPGA routing change as the cluster size changes, and how many inputs should the programmable routing provide to each cluster? We first show that logic clusters require fewer inputs from the routing than current commercial FPGAs provide. Secondly, we show that for best area-efficiency the flexibility of FPGA routing should be significantly reduced as the cluster size is increased. Finally, we find that clusters containing between 1 and 8 look-up tables all provide reasonable area-efficiency, as long as the number of cluster inputs and the FPGA routing flexibility are chosen appropriately.