DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.587742
Circuit designers can efficiently verify designs at the bit and word levels in one graph-based data structure. The authors present the representation technique, manipulation algorithms for K*BMDs, and experimental results comparing them with other data structures.
Citation:
Rolf Drechsler, Bernd Becker, Stefan Ruppertz, "The K*BMD: A Verification Data Structure," IEEE Design and Test of Computers, vol. 14, no. 2, pp. 51-59, Apr.-June 1997, doi:10.1109/54.587742 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||