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Observable Time Windows: Verifying High-Level Synthesis Results
April-June 1997 (vol. 14 no. 2)
pp. 40-50
ASCII Text
x 
 
Reinaldo A. Bergamaschi, Salil Raje, "Observable Time Windows: Verifying High-Level Synthesis Results," IEEE Design and Test of Computers, vol. 14, no. 2, pp. 40-50, April-June, 1997.
 
 
BibTex
x
 
@article{ 10.1109/54.587740,
author = {Reinaldo A. Bergamaschi and Salil Raje},
title = {Observable Time Windows: Verifying High-Level Synthesis Results},
journal ={IEEE Design and Test of Computers},
volume = {14},
number = {2},
issn = {0740-7475},
year = {1997},
pages = {40-50},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.587740},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Observable Time Windows: Verifying High-Level Synthesis Results
IS - 2
SN - 0740-7475
SP40
EP50
EPD - 40-50
A1 - Reinaldo A. Bergamaschi,
A1 - Salil Raje,
PY - 1997
VL - 14
JA - IEEE Design and Test of Computers
ER -
 

Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.

Citation:
Reinaldo A. Bergamaschi, Salil Raje, "Observable Time Windows: Verifying High-Level Synthesis Results," IEEE Design and Test of Computers, vol. 14, no. 2, pp. 40-50, Apr.-June 1997, doi:10.1109/54.587740
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