Collateral ASIC Test

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January-March 1997 (vol. 14 no. 1)

pp. 55-63

	ASCII Text	x
	Al Bailey, Tim Lada, Jim Preston, "Collateral ASIC Test," IEEE Design and Test of Computers, vol. 14, no. 1, pp. 55-63, January-March, 1997.

	BibTex	x
	@article{ 10.1109/54.573368, author = {Al Bailey and Tim Lada and Jim Preston}, title = {Collateral ASIC Test}, journal ={IEEE Design and Test of Computers}, volume = {14}, number = {1}, issn = {0740-7475}, year = {1997}, pages = {55-63}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.573368}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Collateral ASIC Test IS - 1 SN - 0740-7475 SP55 EP63 EPD - 55-63 A1 - Al Bailey, A1 - Tim Lada, A1 - Jim Preston, PY - 1997 KW - ASIC Test KW - Boundary-scan Test KW - Reading Status KW - Test Cost Reduction KW - Test Standardization VL - 14 JA - IEEE Design and Test of Computers ER -

Al Bailey

Tim Lada

Jim Preston

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.573368

ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. This paper presents an extension of the boundary-scan technique currently implemented to provide ASIC testability. The concept of Collateral ASIC Test (method and logic) implemented in a boundary-scan device is described as well as the test process standardization implied by this new approach to ASIC design and testing.

Index Terms:

ASIC Test, Boundary-scan Test, Reading Status, Test Cost Reduction, Test Standardization

Citation:

Al Bailey, Tim Lada, Jim Preston, "Collateral ASIC Test," IEEE Design and Test of Computers, vol. 14, no. 1, pp. 55-63, Jan.-Mar. 1997, doi:10.1109/54.573368

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