Transparent Logic Modeling in VHDL May/June 1990 (vol. 7 no. 3) pp. 42-48
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.56466
Modeling conventions and VHDL (VHSIC hardware description language) library techniques for transparently mapping between multivalued logic systems without modifying the model itself is described. Using these conventions and the VHDL library system, designers can choose any logic system compatible with the models and use if for simulation. Also described are some of the requirements the multivalued logic systems must satisfy.
Citation:
Joanne E. DeGroat, "Transparent Logic Modeling in VHDL," IEEE Design and Test of Computers, vol. 7, no. 3, pp. 42-48, May/June 1990, doi:10.1109/54.56466 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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