How ATE Planning Affects LSI Manufacturing Cost

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Winter 1996 (vol. 13 no. 4)

pp. 66-73

	ASCII Text	x
	Koji Nakamae, Homare Sakamoto, Hiromu Fujioka, "How ATE Planning Affects LSI Manufacturing Cost," IEEE Design and Test of Computers, vol. 13, no. 4, pp. 66-73, Winter, 1996.

	BibTex	x
	@article{ 10.1109/54.544538, author = {Koji Nakamae and Homare Sakamoto and Hiromu Fujioka}, title = {How ATE Planning Affects LSI Manufacturing Cost}, journal ={IEEE Design and Test of Computers}, volume = {13}, number = {4}, issn = {0740-7475}, year = {1996}, pages = {66-73}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.544538}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - How ATE Planning Affects LSI Manufacturing Cost IS - 4 SN - 0740-7475 SP66 EP73 EPD - 66-73 A1 - Koji Nakamae, A1 - Homare Sakamoto, A1 - Hiromu Fujioka, PY - 1996 KW - VLSI manufacturing system KW - test cost KW - LSI tester KW - evaluation VL - 13 JA - IEEE Design and Test of Computers ER -

Koji Nakamae

Homare Sakamoto

Hiromu Fujioka

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.544538

The authors describe ATE planning effects on the total LSI manufacturing costs through simulation analysis, which uses a combination of the event-scheduling approach and detailed parametric models. They show that the method is useful in predicting the cost effects of ATE planning in the LSI manufacturing system.

Index Terms:

VLSI manufacturing system, test cost, LSI tester, evaluation

Citation:

Koji Nakamae, Homare Sakamoto, Hiromu Fujioka, "How ATE Planning Affects LSI Manufacturing Cost," IEEE Design and Test of Computers, vol. 13, no. 4, pp. 66-73, Dec. 1996, doi:10.1109/54.544538

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