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Spanning the Product Life Cycle: RASSP DFT
Fall 1996 (vol. 13 no. 3)
pp. 32-42
ASCII Text
x 
 
Richard M. Sedmak, John S. Evans, "Spanning the Product Life Cycle: RASSP DFT," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 32-42, Fall, 1996.
 
 
BibTex
x
 
@article{ 10.1109/54.536094,
author = {Richard M. Sedmak and John S. Evans},
title = {Spanning the Product Life Cycle: RASSP DFT},
journal ={IEEE Design and Test of Computers},
volume = {13},
number = {3},
issn = {0740-7475},
year = {1996},
pages = {32-42},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.536094},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Spanning the Product Life Cycle: RASSP DFT
IS - 3
SN - 0740-7475
SP32
EP42
EPD - 32-42
A1 - Richard M. Sedmak,
A1 - John S. Evans,
PY - 1996
KW - BIST
KW - design for testability
KW - rapid prototyping
KW - RASSP
KW - signal processors
KW - test strategy
VL - 13
JA - IEEE Design and Test of Computers
ER -
 
This article describes a design for testability process, which is highly automated, hierarchical, and spans the entire life cycle. The process was developed for the DoD's RASSP Program and contributes significantly to the RASSP goals of 4x improvement in cycle time, design quality, and life cycle costs.
Index Terms:
BIST, design for testability, rapid prototyping, RASSP, signal processors, test strategy
Citation:
Richard M. Sedmak, John S. Evans, "Spanning the Product Life Cycle: RASSP DFT," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 32-42, Sept. 1996, doi:10.1109/54.536094
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