DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.485783
An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate, component functional defect rate and test coverage. A new Yield model which accounts for the clustering of solder defects is introduced, and a first-order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given.
Index Terms:
test costs , board faults, dft , board test coverage, yield
Citation:
Mick M.v. Tegethoff, Tom W. Chen, "Sensitivity Analysis of Critical Parameters in Board Test," IEEE Design and Test of Computers, vol. 13, no. 1, pp. 58-63, Mar. 1996, doi:10.1109/54.485783 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||