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Saving Power by Synthesizing Gated Clocks for Sequential Circuits
October/December 1994 (vol. 11 no. 4)
pp. 32-41
ASCII Text
x 
 
Luca Benini, Polly Siegel, Giovanni De Micheli, "Saving Power by Synthesizing Gated Clocks for Sequential Circuits," IEEE Design and Test of Computers, vol. 11, no. 4, pp. 32-41, October/December, 1994.
 
 
BibTex
x
 
@article{ 10.1109/54.329451,
author = {Luca Benini and Polly Siegel and Giovanni De Micheli},
title = {Saving Power by Synthesizing Gated Clocks for Sequential Circuits},
journal ={IEEE Design and Test of Computers},
volume = {11},
number = {4},
issn = {0740-7475},
year = {1994},
pages = {32-41},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.329451},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IS - 4
SN - 0740-7475
SP32
EP41
EPD - 32-41
A1 - Luca Benini,
A1 - Polly Siegel,
A1 - Giovanni De Micheli,
PY - 1994
VL - 11
JA - IEEE Design and Test of Computers
ER -
 

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area.

Citation:
Luca Benini, Polly Siegel, Giovanni De Micheli, "Saving Power by Synthesizing Gated Clocks for Sequential Circuits," IEEE Design and Test of Computers, vol. 11, no. 4, pp. 32-41, Oct. 1994, doi:10.1109/54.329451
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