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Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling
January/March 1994 (vol. 11 no. 1)
pp. 18-26
ASCII Text
x 
 
Sungho Kang, Stephen A. Szygenda, "Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling," IEEE Design and Test of Computers, vol. 11, no. 1, pp. 18-26, January/March, 1994.
 
 
BibTex
x
 
@article{ 10.1109/54.262319,
author = {Sungho Kang and Stephen A. Szygenda},
title = {Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling},
journal ={IEEE Design and Test of Computers},
volume = {11},
number = {1},
issn = {0740-7475},
year = {1994},
pages = {18-26},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.262319},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling
IS - 1
SN - 0740-7475
SP18
EP26
EPD - 18-26
A1 - Sungho Kang,
A1 - Stephen A. Szygenda,
PY - 1994
VL - 11
JA - IEEE Design and Test of Computers
ER -
 

To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.

Citation:
Sungho Kang, Stephen A. Szygenda, "Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling," IEEE Design and Test of Computers, vol. 11, no. 1, pp. 18-26, Jan. 1994, doi:10.1109/54.262319
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