DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.211530
For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples.
Citation:
Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja, "A Tutorial on Built-In Self-Test, Part 2: Applications," IEEE Design and Test of Computers, vol. 10, no. 2, pp. 69-77, Apr. 1993, doi:10.1109/54.211530 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||