Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing April/June 1993 (vol. 10 no. 2) pp. 13-23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.211524
A rapid failure analysis method for high-density CMOS static RAMs (SRAMs) that uses realistic defect modeling and the results of functional and I/sub DDQ/ testing is presented. The key to the method is the development of a defect-to-signature vocabulary through inductive fault analysis. Results indicate that the method can efficiently debug the multimegabit-memory manufacturing process.
Citation:
Samir Naik, Frank Agricola, Wojciech Maly, "Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing," IEEE Design and Test of Computers, vol. 10, no. 2, pp. 13-23, Apr. 1993, doi:10.1109/54.211524 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||