Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters

Design&Test
1993
Issue No. 2 - April/June
Abstract - Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters

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April/June 1993 (vol. 10 no. 2)

pp. 6-12

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	Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima, "Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters," IEEE Design and Test of Computers, vol. 10, no. 2, pp. 6-12, April/June, 1993.

	BibTex	x
	@article{ 10.1109/54.211523, author = {Masaki Tsukude and Kazutami Arimoto and Hideto Hidaka and Yasuhiro Konishi and Masanori Hayashikoshi and Katsuhiro Suma and Kazuyasu Fujishima}, title = {Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters}, journal ={IEEE Design and Test of Computers}, volume = {10}, number = {2}, issn = {0740-7475}, year = {1993}, pages = {6-12}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.211523}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters IS - 2 SN - 0740-7475 SP6 EP12 EPD - 6-12 A1 - Masaki Tsukude, A1 - Kazutami Arimoto, A1 - Hideto Hidaka, A1 - Yasuhiro Konishi, A1 - Masanori Hayashikoshi, A1 - Katsuhiro Suma, A1 - Kazuyasu Fujishima, PY - 1993 VL - 10 JA - IEEE Design and Test of Computers ER -

Masanori Hayashikoshi

Katsuhiro Suma

Kazuyasu Fujishima

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.211523

Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V/sub CC/ to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V/sub CC/ levels during the water sort test (WT) and the final shipping test (FT).

Citation:

Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima, "Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters," IEEE Design and Test of Computers, vol. 10, no. 2, pp. 6-12, Apr. 1993, doi:10.1109/54.211523

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