loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Shortening the Design Cycle for Programmable Logic
October/December 1992 (vol. 9 no. 4)
pp. 40-50
ASCII Text
x 
 
Steven H. Kelem, Jorge P. Seidel, "Shortening the Design Cycle for Programmable Logic," IEEE Design and Test of Computers, vol. 9, no. 4, pp. 40-50, October/December, 1992.
 
 
BibTex
x
 
@article{ 10.1109/54.173332,
author = {Steven H. Kelem and Jorge P. Seidel},
title = {Shortening the Design Cycle for Programmable Logic},
journal ={IEEE Design and Test of Computers},
volume = {9},
number = {4},
issn = {0740-7475},
year = {1992},
pages = {40-50},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.173332},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Shortening the Design Cycle for Programmable Logic
IS - 4
SN - 0740-7475
SP40
EP50
EPD - 40-50
A1 - Steven H. Kelem,
A1 - Jorge P. Seidel,
PY - 1992
VL - 9
JA - IEEE Design and Test of Computers
ER -
 

X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis.

Citation:
Steven H. Kelem, Jorge P. Seidel, "Shortening the Design Cycle for Programmable Logic," IEEE Design and Test of Computers, vol. 9, no. 4, pp. 40-50, Oct. 1992, doi:10.1109/54.173332
Usage of this product signifies your acceptance of the Terms of Use.