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A Fast Partitioning Method for PLA-Based FPGAs
October/December 1992 (vol. 9 no. 4)
pp. 34-39
ASCII Text
x 
 
Zafar Hasan, David Harrison, Maciej Ciesielski, "A Fast Partitioning Method for PLA-Based FPGAs," IEEE Design and Test of Computers, vol. 9, no. 4, pp. 34-39, October/December, 1992.
 
 
BibTex
x
 
@article{ 10.1109/54.173331,
author = {Zafar Hasan and David Harrison and Maciej Ciesielski},
title = {A Fast Partitioning Method for PLA-Based FPGAs},
journal ={IEEE Design and Test of Computers},
volume = {9},
number = {4},
issn = {0740-7475},
year = {1992},
pages = {34-39},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.173331},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - A Fast Partitioning Method for PLA-Based FPGAs
IS - 4
SN - 0740-7475
SP34
EP39
EPD - 34-39
A1 - Zafar Hasan,
A1 - David Harrison,
A1 - Maciej Ciesielski,
PY - 1992
VL - 9
JA - IEEE Design and Test of Computers
ER -
 

A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner.

Citation:
Zafar Hasan, David Harrison, Maciej Ciesielski, "A Fast Partitioning Method for PLA-Based FPGAs," IEEE Design and Test of Computers, vol. 9, no. 4, pp. 34-39, Oct. 1992, doi:10.1109/54.173331
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