A graph-based technology-mapping package for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm, DAG-Map, carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fan-out-free trees. As a preprocessing phase of DAG-Map, a general algorithm called DMIG, which transforms an arbitrary n-node network into a two-input network with only an O(1) factor increase in network depth, is introduced. A matching-based technique that minimizes area without increasing network delay, and is used in the postprocessing phase of DAG-Map is discussed. DAG-Map is compared with previous FPGA mapping algorithms on a set of logic synthesis benchmarks. The experimental results show that, on average, DAG-Map reduces both network delay and the number of look-up tables.