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A VHDL Fault Diagnosis Tool Using Functional Fault Models
April/June 1992 (vol. 9 no. 2)
pp. 33-41

The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault diagnosis tool (VFDT) are discussed. Given a VHDL description, a compiler creates an internal representation suitable for simulation and fault diagnosis. VFDT diagnoses faults in this representation hierarchically using the stuck-at fault model at the first level and the arbitrary-failure model at the second level. It reasons from first principles by means of constraint suspension. Examples of fault diagnosis using the VFDT are described.

Citation:
Vijay Pitchumani, Pankaj Mayor, Nimish Radia, "A VHDL Fault Diagnosis Tool Using Functional Fault Models," IEEE Design and Test of Computers, vol. 9, no. 2, pp. 33-41, Apr. 1992, doi:10.1109/54.143144
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