DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.107201
A self-testing cryptographic coprocessing chip that provides high security for any data protected through its use is described. The design philosophy and chip architecture are examined. Detailed design and test methods and solutions are given, and it is explained why the chip's design interacts well in networks and with secure hard disks.
Citation:
Karlheinz Hafner, Hartmut Ritter, Thomas M. Schwair, Stefan Wallstab, Michael Deppermann, Juergen Gessner, Stefan Koesters, Wolf-Deitrich Moeller, Gerd Sandweg, "Design and Test of an Integrated Cryptochip," IEEE Design and Test of Computers, vol. 8, no. 4, pp. 6-17, Oct. 1991, doi:10.1109/54.107201 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||