Will Physical Scalability Sabotage Performance Gains?

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Will Physical Scalability Sabotage Performance Gains?

September 1997 (vol. 30 no. 9)

pp. 37-39

	ASCII Text	x
	Doug Matzke, "Will Physical Scalability Sabotage Performance Gains?," Computer, vol. 30, no. 9, pp. 37-39, September, 1997.

	BibTex	x
	@article{ 10.1109/2.612245, author = {Doug Matzke}, title = {Will Physical Scalability Sabotage Performance Gains?}, journal ={Computer}, volume = {30}, number = {9}, issn = {0018-9162}, year = {1997}, pages = {37-39}, doi = {http://doi.ieeecomputersociety.org/10.1109/2.612245}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - Computer TI - Will Physical Scalability Sabotage Performance Gains? IS - 9 SN - 0018-9162 SP37 EP39 EPD - 37-39 A1 - Doug Matzke, PY - 1997 VL - 30 JA - Computer ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.612245

The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles.

Citation:

Doug Matzke, "Will Physical Scalability Sabotage Performance Gains?," Computer, vol. 30, no. 9, pp. 37-39, Sept. 1997, doi:10.1109/2.612245

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