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Design Issues in Division and Other Floating-Point Operations
February 1997 (vol. 46 no. 2)
pp. 154-161
Abstract—Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications. However, in the worst case, a high latency hardware floating-point divider can contribute an additional 0.50 CPI to a system executing SPECfp92 applications. This paper presents the system performance impact of floating-point division latency for varying instruction issue rates. It also examines the performance implications of shared multiplication hardware, shared square root, on-the-fly rounding and conversion, and fused functional units. Using a system level study as a basis, it is shown how typical floating-point applications can guide the designer in making implementation decisions and trade-offs.
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Index Terms:
Benchmarks, computer arithmetic, division, floating-point, multiplication, square root, system performance.
Citation:
Stuart F. Oberman, Michael J. Flynn, "Design Issues in Division and Other Floating-Point Operations," IEEE Transactions on Computers, vol. 46, no. 2, pp. 154-161, Feb. 1997, doi:10.1109/12.565590
