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Area-Time Optimal Adder Design
May 1990 (vol. 39 no. 5)
pp. 666-675
A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS.
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Index Terms:
area-time optimal adder design; VLSI parallel adder; modular design; component cells; static CMOS; dynamic programming; floating-point processor; 66 bit; adders; CMOS integrated circuits; digital arithmetic; dynamic programming; logic design; VLSI.
Citation:
B.W.Y. Wei, C.D. Thompson, "Area-Time Optimal Adder Design," IEEE Transactions on Computers, vol. 39, no. 5, pp. 666-675, May 1990, doi:10.1109/12.53579
