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An Asynchronous Dataflow FPGA Architecture
November 2004 (vol. 53 no. 11)
pp. 1376-1392
We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow functions that obey a token-based compute model. We implement these dataflow functions using finely pipelined asynchronous circuits that achieve high computation rates. This asynchronous dataflow FPGA architecture maintains most of the performance benefits of a custom asynchronous design, while also providing postfabrication logic reconfigurability. We report results for two asynchronous dataflow FPGA designs that operate at up to 400 MHz in a typical TSMC 0.25\mu m CMOS process.
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Index Terms:
Asynchronous/synchronous operation, dataflow architectures, gate arrays, reconfigurable hardware.
Citation:
John Teifel, Rajit Manohar, "An Asynchronous Dataflow FPGA Architecture," IEEE Transactions on Computers, vol. 53, no. 11, pp. 1376-1392, Nov. 2004, doi:10.1109/TC.2004.88
