10th Working Conference on Reverse Engineering (WCRE 2003)
Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables
Victoria, B.C., Canada
November 13-November 17
ISBN: 0-7695-2027-8
EPIC (Explicitly Parallel Instruction Computing) architectures, exemplified by the Intel Itanium, support a number of advanced architectural features, such as explicit instruction-level parallelism, instruction predication, and speculative loads from memory. However, compiler optimizations to take advantage of such architectural features can profoundly restructure the program's code, making it potentially difficult to reconstruct the original program logic from an optimized Itanium executable. This paper describes techniques to undo some of the effects of such optimizations and thereby improve the quality of reverse engineering such executables.
Citation:
Noah Snavely, Saumya Debray, Gregory Andrews, "Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables," wcre, pp.4, 10th Working Conference on Reverse Engineering (WCRE 2003), 2003