loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Sixth IEEE Workshop on Applications of Computer Vision (WACV'02)
Pattern Alignment Method Based on Consistency Among Local Registration Candidates for LSI Wafer Pattern Inspection
Orlando, Florida
December 03-December 04
ISBN: 0-7695-1858-3
Takashi Hiroi, Production Engineering Research Laboratory, Hitachi Ltd.
Chie Shishido, Production Engineering Research Laboratory, Hitachi Ltd.
Masahiro Watanabe, Production Engineering Research Laboratory, Hitachi Ltd.
This paper reports an image-processing algorithm for robust inspection of LSI wafer patterns using SEM. In order to detect defects in a regular LSI pattern, a pair of long patterns are compared, blocked images are aligned, and defects are judged using the aligned images. The LSI wafer pattern is defined to consist of blank space, fine repetitive patterns, and unique patterns. Distortion of the SEM image is larger than the repetitive pattern pitch, requiring the system to keep track of the alignment in areas without pattern information or in blank space and mitigate the indeterminacy of repetitive patterns. To satisfy these requirements, a two-layer algorithm is proposed. The lower layer calculates registration candidates in each block, and the upper layer determines the correct registration route, i.e. the chain of the correct registration, using candidate information in all the related blocks. Experimental evaluations confirm that most pattern cases can be inspected correctly using the proposed SEM inspection system.
Citation:
Takashi Hiroi, Chie Shishido, Masahiro Watanabe, "Pattern Alignment Method Based on Consistency Among Local Registration Candidates for LSI Wafer Pattern Inspection," wacv, pp.257, Sixth IEEE Workshop on Applications of Computer Vision (WACV'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.